1. Technical Field
The present disclosure relates to a nonvolatile memory comprising at least one bitline and at least one memory cell linked to the bitline, and means for applying a programming voltage to the bitline or for setting the bitline in a floating state.
The present disclosure also relates to a method of programming memory cells in a nonvolatile memory comprising at least two bitlines to which the memory cells are linked, comprising a step of applying a programming voltage to a first bitline and of setting a second bitline in a floating state.
2. Description of the Related Art
FIG. 1 schematically shows, in cross-section, a conventional nonvolatile memory structure M1 integrated in a semiconductor microchip. The memory comprises a semiconductor substrate 10 in which memory cells 12 are formed. The memory cells 12 are linked by contacts 21 to electrically conductive bitlines BL (BLi−1, BLi, BLi+1). The bitlines BL are embedded in a dielectric material 20 that covers the substrate 10. The memory cells 12 linked to a same bitline BLi are isolated from memory cells linked to adjacent bitlines BLi−1, BLi+1 by electrically isolating trenches 11.
Programming data in a group of memory cells generally comprises a step of erasing the group of memory cells, followed by a step of selectively programming memory cells. During the programming step, the bitlines BL linked to memory cells to be programmed receive a programming voltage Vhv, whereas the bitlines linked to memory cells to remain in the erased state are set in a floating state FLT, that is to say, disconnected from the rest of the circuit.
Due to the increasingly strict miniaturization specifications for integrated circuits, the distance separating two bitlines tends to reduce as well. A typical distance between two bitlines is for example 0.24 microns. This reduced distance causes a capacitive coupling between adjacent bitlines, resulting in the appearance of electrical field lines 22 between the bitlines receiving the voltage Vhv and the floating bitlines.
A floating bitline BLi next to a bitline BLi−1 receiving the voltage Vhv finds itself brought to a parasitic potential Vf1 that tends to increase under the effect of capacitive coupling. The capacitive coupling effect is even more pronounced when the floating bitline BLi is surrounded by two lines BLi−1 and BLi+1 receiving the voltage Vhv. The equivalent electrical diagram shown in FIG. 2 shows that in such a case, the potential Vf1 of the bitline BLi may be estimated by means of the following equation:Vf1=2Vhv*C2/(C1+2C2)  (equation 1)
wherein C1 is the capacitive coupling between the bitline BLi and the ground of the circuit, and C2 is the parasitic capacitive coupling between the bitline and each of the adjacent bitlines BLi−1 and BLi+1. In practice, the parasitic potential Vf1 can reach 8 to 9 V for a voltage Vhv on the order of 15 V.
This parasitic potential Vf1 can cause an involuntary injection of electrical charges in erased memory cells, leading to a parasitic programming of these memory cells.
To resolve this problem, the bitlines that do not need to receive the voltage Vhv may be grounded. This solution is however not desirable due to the existence of leakage currents i1 circulating between the memory cells 12 and ground (in particular between the drain regions of the memory cells and ground), and leakage currents i2 circulating between the memory cells receiving the voltage Vhv and the memory cells linked to floating bitlines (currents passing under the isolating trenches 11). The leakage currents i2 are weak, on the nanoampere level, and are limited by the potential Vf1. Grounding the bitlines that should not receive the voltage Vhv would lead to a considerable increase of leakage currents i2, which could reach the microampere level. Such an increase of leakage currents could cause the voltage source supplying the voltage Vhv, such as a charge pump, to collapse.